Most modern computer systems include a controller and a main memory. The speed at which the controller can decode and execute instructions to process data has for some time exceeded the speed at which instructions and data can be transferred from main memory to the controller. In an attempt to reduce the problems cause by this mismatch, most computer systems include a cache memory between the controller and main memory.
The cache memory is used in computer systems to effectively accelerate the execution speed of instructions and commands by the computer controller. Cache memory is relatively small memory compared to the main memory. The cache memory, however, provides much faster access time than the access time associated with the main memory. The cache memory provides quick access to instructions and data that are most frequently used by the controller.
Instructions and data received from the main memory by the controller for execution are also stored in the high speed cache memory. Therefore, the controller has ready access to the most recently executed instructions and data if the same instructions or data be needed again by the controller. When the controller requires an instruction and data a second time, rather than initiating a relatively slow main memory retrieval, the controller quickly retrieves the information from the high speed cache memory.
It is important to keep track of which lines of code and data are stored in the cache memory. One technique is to use TAG cache memory which includes memory locations for storing TAG addresses that correspond to addresses of the particular information stored in the cache memory. The controller generates a request for an instruction of data in the form of an address. Retrievals from main memory are made using the entire memory address. The cache memory is smaller than the main memory. Therefore, only a subset of the entire memory address is required for retrievals from the cache memory. The portion of the entire memory address that is not included within the subset required for retrievals from the cache memory is stored within the corresponding location of the TAG cache memory. The TAG addresses are used to determine when an address generated by the controller is one in which the cache memory contains the requested information. To accomplish this, the address generated by the controller is compared to the TAG addresses. When the address generated by a request from the controller matches a TAG address, then the cache memory contains the requested information, and a TAG hit occurs. If an address generated by the controller fails to match any TAG address, then a TAG miss occurs. When a TAG miss occurs, e.g. the requested information is not contained in the cache memory, a memory cycle to the main memory must be generated to obtain the requested information. A memory cycle to the main memory requires much more time than a memory cycle to the cache memory.
Many computer systems also include prefetch cache memory in which prefetch information, e.g. information that the controller does not immediately need, is stored. Prefetch information is requested and retrieved from main memory and stored in the prefetch memory because a high probability exists that the controller will request the information in the near future. The stored prefetch information is available to the controller in prefetch cache memory. Therefore, the controller does not need to retrieve this information from the main memory in the future.
Cache memory and prefetch cache memory in present computer systems exist in separate RAM (random access memory). It is generally believed that by physically separating the two types of cache, the performance of the computer system is enhanced. However, the requirement of separate RAM for each of the types of cache requires at least two separate RAM integrated circuits, which increases the cost of the computer system.
It is desirable to have a computer system in which cache memory and prefetch cache memory can be located within a single RAM, and therefore be less expensive. Additionally, it is desirable that the size of the prefetch cache memory be variably adjusted by a controller within the computer system to allow the controller to optimize the prefetch cache size depending upon the task being performed by the controller.